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LHF32KZM
Table 2. Pin Descriptions
5
Symbol
A 0 -A 21
DQ 0 -DQ 15
CE 0 #,
CE 1 #
RP#
OE#
WE#
STS
WP#
BYTE#
V PP
V CC
GND
NC
Type
INPUT
INPUT/
OUTPUT
INPUT
INPUT
INPUT
INPUT
OPEN
DRAIN
OUTPUT
INPUT
INPUT
SUPPLY
SUPPLY
SUPPLY
Name and Function
ADDRESS INPUTS: Inputs for addresses during read and write operations. Addresses are
internally latched during a write cycle.
A 0 : Byte Select Address. Not used in x16 mode(can be floated).
A 1 -A 4 : Column Address. Selects 1 of 16 bit lines.
A 5 -A 15 : Row Address. Selects 1 of 2048 word lines.
A 16 -A 21 : Block Address.
DATA INPUT/OUTPUTS:
DQ 0 -DQ 7 :Inputs data and commands during CUI write cycles; outputs data during memory
array, status register, query, and identifier code read cycles. Data pins float to high-
impedance when the chip is deselected or outputs are disabled. Data is internally latched
during a write cycle.
DQ 8 -DQ 15 :Inputs data during CUI write cycles in x16 mode; outputs data during memory
array read cycles in x16 mode; not used for status register, query and identifier code read
mode. Data pins float to high-impedance when the chip is deselected, outputs are
disabled, or in x8 mode(Byte#=V IL ). Data is internally latched during a write cycle.
CHIP ENABLE: Activates the device’s control logic, input buffers decoders, and sense
amplifiers. Either CE 0 # or CE 1 # V IH deselects the device and reduces power consumption
to standby levels. Both CE 0 # and CE 1 # must be V IL to select the devices.
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets
internal automation. RP# V IH enables normal operation. When driven V IL , RP# inhibits
write operations which provides data protection during power transitions. Exit from deep
power-down sets the device to read array mode.
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are
latched on the rising edge of the WE# pulse.
STS (RY/BY#): Indicates the status of the internal WSM. When configured in level mode
(default mode), it acts as a RY/BY# pin. When low, the WSM is performing an internal
operation (block erase, full chip erase, (multi) word/byte write or block lock-bit
configuration). STS High Z indicates that the WSM is ready for new commands, block
erase is suspended, and (multi) word/byte write is inactive, (multi) word/byte write is
suspended or the device is in deep power-down mode. For alternate configurations of the
STATUS pin, see the Configuration command.
WRITE PROTECT: Master control for block locking. When V IL, Locked blocks can not be
erased and programmed, and block lock-bits can not be set and reset.
BYTE ENABLE: BYTE# V IL places device in x8 mode. All data is then input or output on
DQ 0-7 , and DQ 8-15 float. BYTE# V IH places the device in x16 mode , and turns off the A 0
input buffer.
BLOCK ERASE, FULL CHIP ERASE, (MULTI) WORD/BYTE WRITE, BLOCK LOCK-
BIT CONFIGURATION POWER SUPPLY: For erasing array blocks, writing bytes or
configuring block lock-bits. With V PP ≤ V PPLK , memory contents cannot be altered. Block
erase, full chip erase, (multi) word/byte write and block lock-bit configuration with an invalid
V PP (see DC Characteristics) produce spurious results and should not be attempted.
DEVICE POWER SUPPLY: Internal detection configures the device for 2.7V or 3.3V
operation. To switch from one voltage to another, ramp V CC down to GND and then ramp
V CC to the new voltage. Do not float any power pins. With V CC ≤ V LKO , all write attempts to
the flash memory are inhibited. Device operations at invalid V CC voltage (see DC
Characteristics) produce spurious results and should not be attempted.
GROUND: Do not float any ground pins.
NO CONNECT: Lead is not internal connected; it may be driven or floated.
Rev. 1.6
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